In general, vias are vertical metal interconnect pathways to electrically connect a first metal layer to a second metal layer in a semiconductor device. Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) circuits include interconnect structures where vias connect metal layers in different levels. Vias and metal layers (also referred to as wires) can be formed in a dual damascene process, where via openings and trenches are formed in a dielectric layer followed by deposition of the conductive metal materials to form the vias and metal layers.
Metal interconnects or vias that are fully aligned to a first metallization level (M(x)) and a second metallization level (M(x+1)) are referred to as fully aligned vias (FAVs). A fully aligned process increases the overlay margin along both axes (e.g., perpendicular and parallel to an interconnect line below). A self-aligned process increases the overlay margin along one axis, but not two. As component size decreases in VLSI and ULSI devices problems associated with small distances between conductive structures, such as, for example, increased line resistance, increased variations in via resistance and shorting, have been encountered.
Accordingly, there is a need for methods and structures for forming FAVs which address problems with isolation of the adjacent conductive structures.